1. Field of the Invention
The present invention relates to a driver circuit. The present invention relates to, for example, a Serializer/De-serializer (hereinafter referred to as “Serdes”) macro, which is a high-speed interface macro to convert a low-speed parallel signal into a high-speed serial signal and output the converted high-speed serial signal, and/or to convert a high-speed serial signal into a low-speed parallel signal and output the converted low-speed parallel signal, and in particular to a driver circuit that outputs a serial signal.
2. Description of Related Art
In recent years, as the telecommunication technology has rapidly advanced, the data transmission speed has become increasingly faster. Since the Serdes macro belongs to the field of high-speed, large-capacity transmission technology, the demand for the increase in speed has especially grown. Further, for the high-speed data transmission, it has been desired to develop a technology for sending data having a large amplitude capable of withstanding attenuation caused by long-distance transmission, let alone short-distance transmission.
To realize a high-speed and large-amplitude operation, it is necessary to form a circuit by using transistors capable of operating at a high speed (low withstand voltage) and to connect the circuit to a high-voltage power supply. For example, up to the conventional speed of 3 Gbps, it is possible to realize such a circuit by forming the pre-driver by low-withstand-voltage (high-speed) transistors and connecting it to a low-voltage power supply, and forming the main-driver by high-withstand-voltage (low-speed) transistors and connecting it to a high-voltage power supply. However, to further increase the data transmission speed to at least twice the conventional speed, i.e., to 6 Gbps or faster, it is necessary to form the pre-driver by low-withstand-voltage (high-speed) transistors and connecting it to a low-voltage power supply, and form the main-driver by low-withstand-voltage (high-speed) transistors and connecting it to a high-voltage power supply.
FIG. 8 shows a circuit diagram of a conventional driver circuit disclosed in Japanese Unexamined Patent Application Publication No. 2001-257579 (Patent document 1). In a driver circuit shown in FIG. 8, a third resistor R300 is connected between the fourth power supply VDDE and the positive-phase output terminal 100, and a fourth resistor R400 is connected between the fourth power supply VDDE and the negative-phase output terminal 200. Further, this driver circuit 900 also includes an output stage 600 and a level shift circuit 700.
The output stage 600 includes a first N-channel MOS transistor N1, a second N-channel MOS transistor N2 and a third N-channel MOS transistor N3. The drain of the first N-channel MOS transistor N1 is connected to the positive-phase output terminal 100. The drain of the second N-channel MOS transistor N2 is connected to the negative-phase output terminal 200. The source of the third N-channel MOS transistor N3 is grounded and the gate is connected to the first power supply 300. Further, the drain of the third N-channel MOS transistor N3 is connected to the sources of the first and second N-channel MOS transistors N1 and N2.
The level shift circuit 700 includes a first resistor R100, a second resistor R200, a fourth N-channel MOS transistor N4, a fifth N-channel MOS transistor N5, and a sixth N-channel MOS transistor N6. A first resistor R100 is connected between the second power supply VDDI and the gate of the first N-channel MOS transistor N1. A second resistor R200 is connected between the second power supply VDDI and the gate of the second N-channel MOS transistor N2. The drain of the fourth N-channel MOS transistor N4 is connected to the gate of the first N-channel MOS transistor N1. The drain of the fifth N-channel MOS transistor N5 is connected to the gate of the second N-channel MOS transistor N2. The source of the sixth N-channel MOS transistor N6 is grounded and the gate is connected to the third power supply 310. Further, the drain of the sixth N-channel MOS transistor N6 is connected to the sources of the fourth and fifth N-channel MOS transistors N4 and N5. Further, the gate of the fourth N-channel MOS transistors N4 serves as a positive-phase input terminal 400, and the gate of the fifth N-channel MOS transistors N5 serves as a negative-phase input terminal 500.
Furthermore, the driver circuit 900 also includes a logic circuit 800, and the electrical power consumed in the internal region of the logic circuit 800 is supplied from the second power supply VDDI. This logic circuit 800 supplies input signals to the level shift circuit 700. Note that the driver circuit 900 includes an internal region composed of the logic circuit 800 and the level shift circuit 700, and an external region (output stage 600) in which signals to/from an external LSI circuit(s) is transmitted/received. Note also that the voltage of the power supply VDDI (second power supply) used in the internal region is lower than the voltage of the fourth power supply VDDE, i.e., the power supply used in the external region. Further, the gate oxide film of MOS transistors used in the external region is formed with a thickness larger than that of MOS transistors used in the internal region.
Furthermore, the driver circuit 900 has the differential output stage 600 that outputs a current externally and the resistance-load type differential circuit (level shift circuit 700) at the preceding stage, and this resistance-load type differential circuit (level shift circuit 700) performs conversion so that the signal level of the internal region becomes a higher potential and the amplitude becomes smaller, and outputs the converted signal to the differential output stage 600. As a result, the potential change becomes smaller in comparison to the case where a signal having a power-supply voltage amplitude is input to the differential output stage 600. In this way, the occurrence of potential fluctuations at the drain of the constant-current transistor N3 of the output stage 600 is prevented.
Next, the operation of the driver circuit 900 shown in FIG. 8 is explained hereinafter. In the driver circuit 900 having the configuration shown in FIG. 8, an input terminal 400 and an input terminal 500 are a positive-phase input terminal and a negative-phase input terminal respectively. Further, a logical High level of these input terminals is the same potential as the power supply voltage VDDI in the internal region, and a logical Low level is a ground potential. The transistors N3 and N6 are connected to other NMOS transistors in a current mirror connection, and their gate potentials are determined so that constant currents flow therethrough.
Then, when a High level and a Low level are input to the positive-phase input terminal 400 and the negative-phase input terminal 500 respectively, the transistor N4 is turned on and the transistor N5 is turned off. Therefore, the constant current I2 determined by the transistor N6 flows to the transistor N4, and the drain potential of the transistor N4 thereby becomes (VDDI31 I2×R1). Meanwhile, since no current flows to the transistor N5, the drain potential of the transistor N5 becomes VDDI. Therefore, the transistor N1 is turned off and the transistor N2 is turned on. Accordingly, since the constant current I1 determined by the transistor N3 flows to the transistor N2, the positive-phase output terminal 100 becomes the same potential as the fourth power supply VDDE and outputs a logical High level. Further, the negative-phase output terminal 200 becomes a potential expressed as (fourth power supply VDDE−I1×R4) and outputs a logical Low level.